1. Field of the Invention
The present invention relates to accessing a flat-cell ROM integrated device, and in particular to an improved on/off current ratio improving circuit for the flat-cell array which is capable of increasing an on/off current ratio of a cell which is used for reading a data by removing parasitic capacitance which occurs when selecting and reading a data from a memory cell.
2. Description of the Conventional Art
FIG. 1 illustrates a conventional flat-cell array which includes a virtual ground, which circuit was disclosed in U.S. Pat. No. 5,117,389 (Jun. 26, 1992).
As shown therein, the conventional flat-cell array includes a connection unit 11 for selectively connecting an external ground terminal GND to an internal cell array 12 through a metal line. In the internal cell array 12, a plurality of cells are connected in a matrix form for outputting data through a corresponding cell in accordance with a driving operation of word lines WL[0]-WL[N], and cell selection units 13L and 13R for selecting a corresponding cell by using left and right selection lines L.sub.-- SL and R.sub.-- SL and a plurality of past transistors among two cells connected to a metal bit line MBL and a virtual ground line VGML when a group of cells is selected in accordance with a driving operation of poly word lines WL[0]-WL[n].
The connection unit 11 is provided with a plurality of metal contacts MC0-MC3, and connects a corresponding local bit line and a virtual ground line VGML[N-1], a corresponding local bit line and a metal bit line MBL[N-1], a corresponding local bit line and a virtual ground line VGML[N], and a local bit line and a metal bit line MBL[N], respectively, among a plurality of local bit lines LBL.
The cell array 12 is provided with a plurality of cells (NM.sub.1.1 -NM.sub.1.8)-(NM.sub.n.1 -NM.sub.n.8), each driven by the corresponding word lines WL[0]-WL[N], and each of the local bit lines LBL is connected with each corresponding connecting point of the plurality of cells (NM.sub.1.1 -NM.sub.1.8)-(NM.sub.N.1 -NM.sub.N.8).
The cell selection unit 13R is provided with a plurality of pass NMOS transistors (NM.sub.R.1 -NM.sub.R.4) which connect each of even number cells and each of the corresponding local bit lines LBL, when the right selection line R-SL is driven, so that odd number cells are selected among the plurality of cells (NM.sub.1.1 -NM.sub.1.8)-(NM.sub.N.1 -NM.sub.N.8).
The cell selection unit 13L is provided with a plurality of pass NMOS transistors (NM.sub.L.1 -NM.sub.L.4) which connect each of odd number cells and each of the corresponding local bit lines LBL, when the left selection line L-SL is driven, so that even number cells are selected among the plurality of cells (NM.sub.1.1 -NM.sub.1.8)-(NM.sub.N.1 -NM.sub.N.8).
With reference to FIGS. 2 and 4, the operation of the conventional memory cell array will be described.
The virtual ground line VGML and metal bit line MBL, which are externally and selectively connected, are vertically formed with respect to the poly word line WL. The virtual ground line VGML and the metal bit line MBL are alternately connected to each other.
When one cell is selected from a plurality of cells of the cell array 12, and the data written in the cell is read, one neighboring virtual ground line VGML and one metal bit line MBL are selected, and the remaining virtual ground lines VGML and metal bit lines MBL become an open state (or a floating state). In addition, one word line of the multiple word lines WL[0]-WL[N] is driven, and a cell of a predetermined cell group is selected. Two cells are selected in accordance with the selection of the virtual ground line VGML and the metal bit line MBL, and one cell between the two cells is selected in accordance with a driving operation of the left and right selection lines L.sub.-- SL and R.sub.-- SL.
FIG. 2A illustrates a current flow path when a predetermined cell MN.sub.n.4 is selected from the circuit of FIG. 1. One WL[N] of the word lines WL[0]-WL[N] is driven, and the virtual ground line VGML[N] and the metal bit line MBL[N-1] are selected, and two cells MN.sub.n.4 and NM.sub.n.5 are selected, and a high level current is supplied to the left selection line L.sub.-- SL between the left and right selection lines L.sub.-- SL and R.sub.-- SL, for thus finally selecting a corresponding cell MN.sub.n.4. Therefore, the current flow path is formed as follows: The metal bit line MBL[N-1].fwdarw. the metal contact MC1.fwdarw. the local bit line LBL1.fwdarw. the cell MN.sub.n.4 .fwdarw.the local bit line LBL2.fwdarw. the pass NMOS transistor NM.sub.L.3 .fwdarw. the local bit line LBL3.fwdarw. the metal contact MC2.fwdarw. the virtual ground line VGML[N].
Taking another example, FIG. 2B illustrates another current flow path when a predetermined cell which is a cell NM.sub.n.5 is selected from the circuit of FIG. 1.
As shown therein, differently from FIG. 2A, a high level current is supplied to the right selection line R.sub.-- SL. The other operations are identical to FIG. 2A. Therefore, the current flow path is as follows: The metal bit line MBL[N-1].fwdarw. the metal contact MC1.fwdarw. the local bit line LBL1.fwdarw. the pass NMOS transistor NM.sub.R.2 .fwdarw. the local bit line LBL2.fwdarw. the cell NM.sub.n.5 .fwdarw. the local bit line LBL3.fwdarw. the metal contact MC2.fwdarw. the virtual ground line VGML[N].
The actual current flow path of the cell is not formed as shown in FIGS. 2A and 2B due to parasitic capacitance which exists in the metal bit line MBL and the virtual ground line VGML, remaining as the open state, but variably formed as shown in FIGS. 3a and 3b.
First, with reference to FIG. 3A, the reason of the increase of the off current caused by the parasitic current flow path will be explained.
The metal bit line MBL[N-1], the virtual ground line VGML[N], and the word line WL[N] are selected, and then the left selection line L.sub.-- SL is selected, and the cell NM.sub.R.4 is finally selected. At this time, when a low level data is sequentially written into the cells NM.sub.N.2 and NM.sub.N.3 neighboring with the cell NMN.4, the parasitic capacitance CO formed at the virtual ground line VGML[N-1], which is not selected, is connected to the selected metal bit line MBL[N-1] and the virtual ground line VGML[N], respectively.
If the parasitic capacitance CO has been discharged, and a high level data is written into the selected cell NM.sub.n.4, the off current of the cell NM.sub.n.4 used for reading the high level data is not flown through the ideal current flow path, but is flown through a parasitic current path PCP1 along the external ground terminal GND formed by the discharged parasitic capacitance CO.
Since the current path of the ideal off current the cell NM.sub.n.4 is blocked due to the high level data of the cell NM.sub.n.4 the current becomes zero as shown by the waveform CUR1 of FIG. 4A. However, the operation that the low level data of another cell except for the cell NM.sub.n.4 selected by the parasitic current path PCP1 is read is performed. The amount of the current passing through the metal bit line MBL[N-1], namely the off current is increased as shown by the waveform CUR2 of FIG. 4A.
In addition, the causes of the decrease of the on current due to the parasitic current path will now be explained with reference to FIG. 3B.
The cell NM.sub.n.3 is selected during the selection step as shown in FIG. 3A. When the low level data is sequentially written into the cells NM.sub.n.4 and NM.sub.n.5, respectively, neighboring with the cell NM.sub.n.3, a parasitic capacitance C2 formed in the virtual ground line VGML[N-1] which is not selected is connected to the metal bit line NBL[N-1] and the virtual ground line VGML[N-1], respectively.
At this time, when the parasitic capacitance C2 has been charged, and the low level data is written into the selected cell NM.sub.n.3, the on current of the cell NM.sub.n.3 used for reading the low level data does not maintain a normal value as shown by the waveform CUR3 of FIG. 4B by the parasitic capacitance C2, except for the normal current path. Namely, the on current is decreased as shown by the waveform CUR4.
In the case of the ideal on current, the voltage level at the node N1 becomes almost zero when connecting an external ground terminal GND to the cell NM.sub.n.3 through the virtual ground line VGML[N]. However, the voltage at the node N1 is increased by the voltage charged into the parasitic capacitance C2. When the voltage charged into the parasitic capacitance C2 is discharged, the voltage is charged again by the parasitic current path PCP2, thus the voltage at the node N1 is maintained at a constant level. The voltage difference between the selected cell NM.sub.n.3 and the node N1 is decreased, and the on current flowing at the metal bit line MBL[N-1] is decreased.
In other words, in order to selectively connect the external ground terminal GND of an external memory cell to the node N1, the pass transistor, namely, the NMOS transistors NM.sub.R.1, NM.sub.R.2, NM.sub.L.2, and NM.sub.L.3 must be connected at the terminal of the virtual ground line VGML[N]. Therefore, the node N1 can not have the voltage identical to the external ground terminal GND.
Finally, the on current of the selected cell is decreased, the off current is increased, and the on/off current ratio of the cell is decreased. The capacity of the memory cell is increased due to the decreased on/off current ratio, for thus increasing the parasitic capacitance.
As described above, in the cell array of the conventional flat-cell ROM integration device, a virtual ground line is necessarily used for selectively connecting an external ground terminal GND to the cell array. Since the cells connected to the word lines are connected in series, when the low level data of the cells are sequentially outputted, the parasitic capacitance of the virtual ground line is connected to the metal bit line which is selected together with the parasitic capacitance of the metal bit lines which not selected, for thus decreasing the on/off current ratio. In the memory apparatus which is configured to read the data of the cell based on the difference between the on current and the off current, the decrease of the on/off current causes a sensing time delay, so that the conventional flat-cell array can not be adapted to the low electric power flat-cell memory in which the current of the cell is significantly decreased and the flat-cell memory which requires a high speed sensing time.